//------------------------------------------------------------
//  Filename: tcdm_interface.sv
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2019-10-17 15:48
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
 
interface LINT_IF
#(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32,
    parameter BE_WIDTH   = DATA_WIDTH/8,
    parameter N_VLD_ADDR = 2    
);

    logic                  data_req;
    logic [ADDR_WIDTH-1:0] data_addr;
    logic [BE_WIDTH-1:0]   data_be;
    logic                  data_we;
    logic [DATA_WIDTH-1:0] data_wdata;
    logic [DATA_WIDTH-1:0] data_r_rdata;
    logic                  data_r_valid;
    logic                  data_r_opc;
    logic                  data_gnt;

    modport Master
    (
        output data_req,
        output data_addr,
        output data_be,
        output data_we,
        output data_wdata,
        input  data_r_rdata,
        input  data_r_valid,
        input  data_r_opc,
        input  data_gnt
    );

    modport Slave
    (
        input  data_req,
        input  data_addr,
        input  data_be,
        input  data_we,
        input  data_wdata,
        output data_r_rdata,
        output data_r_valid,
        output data_r_opc,
        output data_gnt
    );
      
endinterface

interface MEMBK_IF
#(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32,
    parameter BE_WIDTH   = DATA_WIDTH/8
);

    logic [ADDR_WIDTH-1:0] mem_addr;
    logic [BE_WIDTH-1:0]   mem_be;
    logic                  mem_we;
    logic [DATA_WIDTH-1:0] mem_wdata;
    logic [DATA_WIDTH-1:0] mem_rdata;
    logic                  mem_en;
    
    modport Master
    (
        output mem_addr,
        output mem_be,
        output mem_we,
        output mem_wdata,
        output mem_en,
        input  mem_rdata
    );

    modport Slave
    (
        input  mem_addr,
        input  mem_be,
        input  mem_we,
        input  mem_wdata,
        input  mem_en,
        output mem_rdata
    );

endinterface


interface APB_BUS
#(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32
);

    logic [ADDR_WIDTH-1:0] paddr;
    logic                  pwrite;
    logic [DATA_WIDTH-1:0] pwdata;
    logic [DATA_WIDTH-1:0] prdata;
    logic                  penable;
    logic                  pready;
    logic                  psel;
    logic                  pslverr;

    modport Master
    (
        output paddr,
        output pwrite,
        output pwdata,
        output penable,
        output psel,
        input  pready,
        input  prdata,
        input  pslverr
    );

    modport Slave
    (
        input  paddr,
        input  pwrite,
        input  pwdata,
        input  penable,
        input  psel,
        output pready,
        output prdata,
        output pslverr
    );

endinterface
